1. Field of the Invention
The present invention relates to analog filter circuits and, in particular, to an analog filter circuit capable of automatic adjustment of filter characteristics.
2. Description of Related Art
A Gm-C filter circuit disclosed in Japanese unexamined patent publication No. H09(1997)-83294 is shown in FIG. 15, wherein the Gm-C filter 100 is adjusted by turning the switches 170 and 190 on and the switches 160 and 180 off. When the center frequency of the Gm-C filter 100 is lower than its ideal frequency, the phase of the filter output lags behind the ideal phase. Based on a phase lag signal output from a phase comparator 110, the count value of an up/down counter 120 is incremented by one. The output current of a fine-adjusting bias current generating circuit 130 is determined by the counter output 270 and an adder 150 adds the output current of the fine-adjusting bias current generating circuit 130 to the output current of a bias current generating circuit 140 and outputs the sum as its output current 310. Here, given that the Gm-C filter 100 is designed so that its center frequency increases by an increase of the bias current, the filter is adjusted by the bias current to decrease the phase lag. By repeating the counter action, eventually, the filter center frequency is adjusted to the ideal filter frequency.